It is well known that extremely high voltages can develop in the vicinity of an integrated circuit due to the build-up of static charges. A high potential may be generated to an input or output buffer of an integrated circuit, which may be caused by a person touching a package pin that is in electrical contact with the input or output buffer. When the electrostatic charges are discharged, a high current is produced at the package nodes of the integrated circuit. Electrostatic discharge (ESD) is a serious problem for semiconductor devices since it has the potential of destroying the entire integrated circuit.
The duration of the ESD transient is very short, typically in the order of nanoseconds, and the conventional circuit breakers cannot react quickly enough to provide adequate protection. For this reason, it has become a known practice to incorporate ESD devices in integrated circuits. Conventionally, bi-directional diode strings are coupled between the package pins to protect the respective circuit. Other ESD devices such as transistors are also being used.
The ESD devices are also widely used between power lines to protect the internal circuit coupled between power lines and to discharge ESD currents to the ground. Typically, a plurality of ESD devices is connected in parallel to increase the maximum ESD current that can flow through, without damaging, the ESD devices. FIGS. 1A and 1B illustrate a top view and a cross-sectional view, respectively, of a conventional ESD protection circuit formed on a silicon-on-insulator (SOI) substrate. The cross-sectional view as shown in FIG. 1B is taken along a plane crossing line G-G′ in FIG. 1A. The SOI substrate includes buried oxide layer 2 underlying semiconductor layer 3 (FIG. 1B), and overlying semiconductor layer 1. Referring to FIG. 1A, the ESD protection circuit includes a plurality of MOS devices having gates 4, source regions 6, and drain regions 8. The channel regions of the MOS devices are located in p-well regions 10 (not shown in FIG. 1A, please refer to FIG. 1B), which are separated from each other by source regions 6 and drain regions 8. STI regions 14 further isolate source regions 6 and drain regions 8. Each of the p-well regions 10 is connected to P+ contacts 16 formed at the opposite ends of gates 4. The P+ contacts 16 are connected to overlying metal lines 18, and are interconnected together. Through metal lines 18, P+ contacts 16 are connected to Vss.
FIG. 1C illustrates an equivalent circuit of the ESD protection circuit shown in FIGS. 1A and 1B. Only the parasitic npn (bipolar) transistors are illustrated, wherein the drains regions 8 act as collectors, the source regions 6 act as emitters, and p-well regions 10 act as bases. Resistors 19 represent the parasitic resistances of p-well 10. In the case an ESD pulse occurs at drain region 8, one or more parasitic npn transistor is turned on, and the ESD current flows through the parasitic npn transistor, so that the voltage on drains 8 may be brought down.
The ESD protection circuit as shown in FIGS. 1A and 1B suffers from drawbacks. It has been found that the ESD protection circuits formed on SOI substrates have worse performance than the similar ESD protection circuits formed on bulk substrates. Particularly, the maximum ESD current that can flow through the ESD protection circuit as shown in FIGS. 1A and 1B is very small, and the ESD protection circuit may easily be damaged. However, SOI substrates are preferred for the good performance, such as low leakage currents, of the integrated circuits formed thereon. This posts a dilemma for designers to choose between high performance and good ESD protection ability. Therefore, new methods are needed to improve the ESD protection ability of ESD protection circuits on SOI substrates.